This application incorporates by reference Taiwanese application Serial No. 88105248, Filed May 4, 1999.
The present invention relates in general to a signal converting device of a chipset, and more particularly to a signal converting device capable of effectively outputting/converting a response signal from a memory interface into a main system interface.
Due to the rapid development on hardware technologies, the clock frequency for the central processing unit (CPU) has improved from several MHz to hundred MHz. For matching the CPU clock frequency, the mainboard has to provide high-frequency clock signals. However, in the prior personal computer (PC), other peripheral devices operate at a slower speed than CPU. The request signal from CPU is faster than the response signal from peripheral devices. As known, the processing rate of CPU is obtained from its inner frequency multiplied by a multiple. For example, 266 MHz is obtained from 66 MHz multiplied by 4, wherein 66 MHz is an inner frequency, and 4 is a multiplier. Nowadays, in current mainboards, the inner frequency of CPU is, for example, 100 MHz, 83 MHz, or 66 MHz. The clock frequency for memory devices, such as dynamic random access memory (DRAM), is, for example, 100 MHz, 83 MHz, 66 MHz or 50 MHz. The clock frequency for the peripheral component interconnection (PCI) interface can be 66 MHz or 33 MHz. The clock frequency for the accelerate graphics port (AGP) interface can be 66 MHz or 133 MHz. There has developed a signal conversion method capable of converting high-frequency request signals from a main system and low-frequency response signals from peripheral devices, such as conversion between 100 MHz/66 MHz or 133 MHz/100 MHz.
Referring to FIG. 1, which illustrates a block diagram for a chipset in a mainboard according to the prior art. In FIG. 1, the clock generator 110 supplies the chipset 100 with two clock signals CLK-A and CLK-B of different frequency. There is an integral ratio between the frequency of the two clock signals CLK-A and CLK-B. For example, when the clock signals CLK-A and CLK-B are respectively 100 MHz and 66 MHz, the integral ratio is about 3:2. That is to say, 3 cycles of the clock signal CLK-A is equal to 2 cycles of the clock signal CLK-B. In the following description, one clock CLK-A cycle refers to one cycle of the clock signal CLK-A.
In the chipset 100, there are three subsystems: main system interface 120, memory interface 130 and AGP/PCI interface 140. The clock signal CLK-A is coupled to a multiplexer (MUX) 122 and then coupled to buffer 124. The output signal CLK-1 from the buffer 124 is coupled to the main system interface 120. The selection signal SEL selects the signals CLK-A or CLK-B via the MUX 132, and then the buffer 134 supplies a signal CLK-2 for the memory interface 130. The signal CLK-B is coupled to the multiplexer (MUX) 142 and then coupled to buffer 144. The output signal CLK-3 from the buffer 144 is input into the AGP/PCI interface 140. The selection signal SEL, which selects different clock signals for the memory interface, is setup by the basic input output system (BIOS) or jump switches on the main board. MUX 122, 132 and 142 are used for making the propagation delay of the three clock signals CLK-1, CLK-2 and CLK-3 approach each other, rather than for selecting signals.
The clock signals CLK-A and CLK-B are coupled to the phase signal generator 150 for supplying signal converting circuits 160, 162 and 164 with phase signals. The number of output signals from the phase signal generator 150 depends on the number of the higher-frequency clock cycles. For example, if 3 cycles of the clock signal CLK-A is equal to 2 cycles of the clock signal CLK-B, the phase signal generator 150, referring to the clock signal CLK-A, generates 3 phase signals PH1, PH2 and PH3. The signal converting circuits 160, 162 and 164 provide a signal propagation path between the main system interface 120, the memory interface 130 and the AGP/PCI interface 140.
FIG. 2 illustrates a timing chart in FIG. 1. FIG. 2 shows the relationship between the clock signals CLK-A and CLK-B and the three phase signals PH1, PH2 and PH3. The clock signals CLK-A and CLK-B are in pseudo synchronization. In other words, the difference between the starting point for the first cycle of the clock signal CLK-A and the first cycle of the clock signal CLK-B is shorter than a predetermined interval; and the difference between the starting point for the (3N+1)th cycle of the clock signal CLK-A and the (2N+1)th cycle of the clock signal CLK-B is also shorter than the predetermined interval, wherein N is a positive integer. The phase signals PH1, PH2 and PH3 appear as enabled signals alternatively, wherein an enabled signal represents a high-level signal or a signal at enabled state. The phase signal PH1 becomes enabled in the (3Mxe2x88x922)th cycle of the phase signal CLK-A. The phase signal PH2 becomes enabled in the (3Mxe2x88x921)th cycle of the phase signal CLK-A. The phase signal PH3 becomes enabled in the 3Mth cycle of the phase signal CLK-A, wherein M is a positive integer.
However, there are also great improvements on peripheral devices. For example, a clock frequency of DRAM may be faster than the inner clock frequency of CPU. The DRAM access rate may be 100 MHz or 133 MHz, and the CPU inner clock frequency may be 66 MHz or 100 MHz. When the DRAM clock frequency is faster than the CPU inner clock frequency, not every response signal can be completely converted and returned to the main system according to the prior art. For example, the response signals generated from the phase signals PH1 and PH3 may occur error and cause signal loss during signal converting. During each signal converting, a signal processing period must be reserved. When the signal processing is in asynchronous mode, it usually happens that only part of signals are completely converted. Now refer to FIG. 3 and 4.
FIG. 3 illustrates a signal converting circuit block diagram shown in FIG. 1, wherein the signal converting circuit represents circuits 160, 162 and 164 in FIG. 1. The input signal SG-I refers to the clock signal CLK-A or CLK-B. The signal converting circuit converts the input signal SG-I into the output signal SG-O. The output signal SG-O also refers to the clock signal CLK-A or CLK-B. The generation of the output signal SG-O relates to the input signal SG-I, the clock signals CLK-A and CLK-B, and the phase signals PH1, PH2 and PH3. Therefore, input signals of the circuit in FIG. 3 further comprise the clock signals CLK-A and CLK-B, and the phase signals PH1, PH2 and PH3.
FIG. 4 shows a timing chart of the signal converting circuit in FIG. 3. The following statement is under the case that the frequency ratio between the clock signals CLK-A and CLK-B is 3:2. In practical circuit design, there must exist a timing delay during signal conversion. If the input signal SG-I is at high frequency, and the output signal is at low frequency, there are three signal conversion types. When the input signal SG-I is the timing A1, A2 and A3 respectively, the output signal is the timing B1, B2 and B3 respectively. Then, the output signal is the timing B4 when the input signal SG-I is the timing A4. However, from FIG. 4, it is clear that the timing B3 is the same as the timing B4. That is to say, the conversion result from the first signal in the current three signals may cover the conversion result from the third signal in the previous three signals, and a signal loss occurs. When the signal conversion from main systems to memory interfaces is slow to fast, such as 66 MHz to 100 MHz, signal conversion can not be completely made.
The prior art has three modes for solving the above signal-loss disadvantage:
1. Abandoning;
That is to say, in computer systems, the main system frequency must always be faster than the memory frequency.
2. Operating the Request Signals in Non-pipeline Mode:
In the non-pipeline mode for the request signals, the next request signal is not accepted until the current response signal becomes ready. Therefore, the request rate and the response rate are lowered and so is the signal conversion rate; and
3. Operating in Non-back-to-back Ready Mode:
In signal converting, even with the request signals operating in pipeline transmission mode, a waiting interval is reserved in successively transmitting ready signal. Because of reserving signal processing interval, each signal can be completely converted and transmitted. In this mode, the signal-converting rate is much lowered because the waiting time for response is increased and the response rate is lowered.
Conventionally, when a back-to-back ready mode is applied and the response rate for DRAM is faster than the request rate for CPU, the ready signal cannot be converted one by one. Because the signal converting is in asynchronous mode, as described above, it may happen that only part of signals can be completely converted. Therefore, this prior art is not a preferred solution for signal converting. The results of signal converting have great impact on the performance of a computer system. If the signal transferring between systems is not well made, it may happen that systems cannot operate properly. The peripheral devices for the main system, for example memory devices, usually have a great effect on the stability of the main system. Therefore, the signal converting device plays an important role on computer systems.
It is therefore an object of the invention to provide an improved method and means for converting signals from memory interfaces at higher frequency into main system interfaces at lower frequency. The present invention can completely convert response signals from high frequency devices to low frequency devices, and solve low efficient and disadvantages caused by asynchronous conversion. The signal loss does not occur when the signal converting circuit is in pseudo synchronization. By employing the present invention, the computer system can work normally and rapidly, in which the frequency for the request signals from main system interfaces is higher than half of the frequency for the response signals from memory interfaces. The computer system is, for example, 100 MHz/133 MHz or 66 MHz/100 MHz.
The present invention achieves the above-mentioned object by providing a chipset with clock signal converting. By applying a signal converting device in the chipset, response signals from memory interfaces can be effectively and correctly converted and output. The signal converting device converts an input signal, which refers to a first clock, into an output signal, which refers to a second clock. A period of m first clock cycles is equal to that of n second clock cycles wherein m and n are both smallest positive integers satisfying 2n greater than m greater than n. The first clock comprises m phase signals, each of which alternatively appears as enabled signals. One period for each phase signal appearing as an enabled signal is equal to one first clock cycle. The input signal comprises a first ready head signal and a first ready tail signal.
In the above chipset, a D-type flip-flop is applied to delay the first ready head signal for one first clock cycle to generate an extension ready head signal. Another D-type flip-flop is further applied to delay the first ready tail signal for one first clock cycle to generate an extension ready tail signal. A logic gate is further applied to generate an extension signal. When the extension ready tail signal and a first phase signal of m phase signals both appear as enabled signals, the extension signal is also an enabled signal. A multiplexer selects and then outputs an extension ready tail signal. The extension ready tail signal comes from part of the enabled first ready tail signal delayed for one first clock cycle. When the extension signal and the first ready tail signal both appear as enabled signals, the first ready tail signal is delayed for one first clock cycle; and an extension ready head signal is generated at the same time for synchronously extending the extension ready tail signal and the extension ready head signal. At last, a signal converting circuit receives the first clock, the second clock, the extension ready tail signal, the extension ready tail and the m phase signals, and generates an output signal by the pseudo synchronization between the first clock and the second clock.